UA1ZBE Custom Firmware v1.0

Features:
- VFO mode with direct frequency input
- POCSAG decoder (512/1200 baud) with BCH(31,21) correction
- Full-screen Spectrum analyzer
- FM Radio receiver
- RSSI signal indicator overlay
- Custom boot splash (UA1ZBE / POCSAG pager / build date)

Architecture:
- app/mode.c — mode dispatcher (VFO/POCSAG/Spectrum/FM)
- app/boot_splash.c — 2-second boot splash
- app/pocsag/ — POCSAG decoder + BCH correction
- app/display_rssi.c — RSSI indicator
- main.c — entry point with custom init
- syscalls.c — bare-metal _sbrk stub

Build: arm-none-eabi-gcc -Os -flto -Wall -Werror -Wextra
Size: 57.9KB Flash / 3.6KB RAM

Controls:
- 0-9: Direct frequency input (VFO)
- SK2: POCSAG mode
- SK1: Spectrum analyzer
- 0: FM Radio
- EXIT: Return to VFO
- F/*: Toggle 512/1200 baud (in POCSAG)

external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_LPC4370_Cortex-M4.dbgconf

@@ -0,0 +1,43 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug Setup
+
+// <o> Release M0 On Connect
+//   <0=> No
+//   <1=> Yes
+// <i> Debugger releases the M0 Application processor from reset when connecting to it.
+ReleaseM0OnConnect = 1;
+
+// <o> Release M0 Sub-System On Connect
+//   <0=> No
+//   <1=> Yes
+// <i> Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only).
+ReleaseM0SubOnConnect = 1;
+
+// <o> Vector Reset
+//   <0=> Processor Only
+//   <1=> Processor and Peripherals
+// <i> Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset
+VecResetWithPeriph = 1;
+
+// </h>
+
+// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
+// <i> Configure the TPIU pin routing as used on your target platform.
+// <o.1> TRACEDATA0
+//   <0=> Pin PF_5
+//   <1=> Pin P7_4
+// <o.2> TRACEDATA1
+//   <0=> Pin PF_6
+//   <1=> Pin P7_5
+// <o.3> TRACEDATA2
+//   <0=> Pin PF_7
+//   <1=> Pin P7_6
+// <o.4> TRACEDATA3
+//   <0=> Pin PF_8
+//   <1=> Pin P7_7
+RoutingTPIU = 0x00000000;
+
+// </h>
+
+// <<< end of configuration section >>>

external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/DebugConfig/LPC-Link2_on-board_LPC4322_Cortex-M4.dbgconf

@@ -0,0 +1,43 @@
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug Setup
+
+// <o> Release M0 On Connect
+//   <0=> No
+//   <1=> Yes
+// <i> Debugger releases the M0 Application processor from reset when connecting to it.
+ReleaseM0OnConnect = 1;
+
+// <o> Release M0 Sub-System On Connect
+//   <0=> No
+//   <1=> Yes
+// <i> Debugger releases the M0 Sub-System from reset when connecting to it (LPC437x only).
+ReleaseM0SubOnConnect = 1;
+
+// <o> Vector Reset
+//   <0=> Processor Only
+//   <1=> Processor and Peripherals
+// <i> Select if to additionally reset peripherals (LCD, USB0, USB1, DMA, SDIO, ETHERNET) after a Vector Reset
+VecResetWithPeriph = 1;
+
+// </h>
+
+// <h> TPIU Pin Routing (TRACECLK fixed on PF_4)
+// <i> Configure the TPIU pin routing as used on your target platform.
+// <o.1> TRACEDATA0
+//   <0=> Pin PF_5
+//   <1=> Pin P7_4
+// <o.2> TRACEDATA1
+//   <0=> Pin PF_6
+//   <1=> Pin P7_5
+// <o.3> TRACEDATA2
+//   <0=> Pin PF_7
+//   <1=> Pin P7_6
+// <o.4> TRACEDATA3
+//   <0=> Pin PF_8
+//   <1=> Pin P7_7
+RoutingTPIU = 0x00000000;
+
+// </h>
+
+// <<< end of configuration section >>>