ua1zbe
a1206d6fd4
Features: - VFO mode with direct frequency input - POCSAG decoder (512/1200 baud) with BCH(31,21) correction - Full-screen Spectrum analyzer - FM Radio receiver - RSSI signal indicator overlay - Custom boot splash (UA1ZBE / POCSAG pager / build date) Architecture: - app/mode.c — mode dispatcher (VFO/POCSAG/Spectrum/FM) - app/boot_splash.c — 2-second boot splash - app/pocsag/ — POCSAG decoder + BCH correction - app/display_rssi.c — RSSI indicator - main.c — entry point with custom init - syscalls.c — bare-metal _sbrk stub Build: arm-none-eabi-gcc -Os -flto -Wall -Werror -Wextra Size: 57.9KB Flash / 3.6KB RAM Controls: - 0-9: Direct frequency input (VFO) - SK2: POCSAG mode - SK1: Spectrum analyzer - 0: FM Radio - EXIT: Return to VFO - F/*: Toggle 512/1200 baud (in POCSAG)
105 lines
3.1 KiB
C
105 lines
3.1 KiB
C
/* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stdbool.h>
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#include "bsp/dp32g030/dma.h"
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#include "bsp/dp32g030/syscon.h"
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#include "bsp/dp32g030/uart.h"
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#include "driver/uart.h"
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static bool UART_IsLogEnabled;
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uint8_t UART_DMA_Buffer[256];
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void UART_Init(void)
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{
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uint32_t Delta;
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uint32_t Positive;
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uint32_t Frequency;
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UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE;
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Delta = SYSCON_RC_FREQ_DELTA;
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Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
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Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
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if (Positive) {
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Frequency += 48000000U;
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} else {
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Frequency = 48000000U - Frequency;
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}
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UART1->BAUD = Frequency / 39053U;
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UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE;
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UART1->RXTO = 4;
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UART1->FC = 0;
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UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE;
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UART1->IE = 0;
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DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE;
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DMA_CH0->MSADDR = (uint32_t)(uintptr_t)&UART1->RDR;
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DMA_CH0->MDADDR = (uint32_t)(uintptr_t)UART_DMA_Buffer;
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DMA_CH0->MOD = 0
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// Source
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| DMA_CH_MOD_MS_ADDMOD_BITS_NONE
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| DMA_CH_MOD_MS_SIZE_BITS_8BIT
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| DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1
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// Destination
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| DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT
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| DMA_CH_MOD_MD_SIZE_BITS_8BIT
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| DMA_CH_MOD_MD_SEL_BITS_SRAM
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;
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DMA_INTEN = 0;
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DMA_INTST = 0
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| DMA_INTST_CH0_TC_INTST_BITS_SET
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| DMA_INTST_CH1_TC_INTST_BITS_SET
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| DMA_INTST_CH2_TC_INTST_BITS_SET
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| DMA_INTST_CH3_TC_INTST_BITS_SET
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| DMA_INTST_CH0_THC_INTST_BITS_SET
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| DMA_INTST_CH1_THC_INTST_BITS_SET
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| DMA_INTST_CH2_THC_INTST_BITS_SET
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| DMA_INTST_CH3_THC_INTST_BITS_SET
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;
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DMA_CH0->CTR = 0
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| DMA_CH_CTR_CH_EN_BITS_ENABLE
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| ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK)
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| DMA_CH_CTR_LOOP_BITS_ENABLE
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| DMA_CH_CTR_PRI_BITS_MEDIUM
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;
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UART1->IF = UART_IF_RXTO_BITS_SET;
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DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE;
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UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE;
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}
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void UART_Send(const void *pBuffer, uint32_t Size)
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{
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const uint8_t *pData = (const uint8_t *)pBuffer;
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uint32_t i;
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for (i = 0; i < Size; i++) {
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UART1->TDR = pData[i];
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while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) {
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}
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}
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}
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void UART_LogSend(const void *pBuffer, uint32_t Size)
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{
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if (UART_IsLogEnabled) {
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UART_Send(pBuffer, Size);
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}
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}
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