ua1zbe
a1206d6fd4
Features: - VFO mode with direct frequency input - POCSAG decoder (512/1200 baud) with BCH(31,21) correction - Full-screen Spectrum analyzer - FM Radio receiver - RSSI signal indicator overlay - Custom boot splash (UA1ZBE / POCSAG pager / build date) Architecture: - app/mode.c — mode dispatcher (VFO/POCSAG/Spectrum/FM) - app/boot_splash.c — 2-second boot splash - app/pocsag/ — POCSAG decoder + BCH correction - app/display_rssi.c — RSSI indicator - main.c — entry point with custom init - syscalls.c — bare-metal _sbrk stub Build: arm-none-eabi-gcc -Os -flto -Wall -Werror -Wextra Size: 57.9KB Flash / 3.6KB RAM Controls: - 0-9: Direct frequency input (VFO) - SK2: POCSAG mode - SK1: Spectrum analyzer - 0: FM Radio - EXIT: Return to VFO - F/*: Toggle 512/1200 baud (in POCSAG)
179 lines
2.3 KiB
Modula-2
179 lines
2.3 KiB
Modula-2
# Copyright 2023 Dual Tachyon
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# https://github.com/DualTachyon
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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[SYSCON]
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@ = 0x40000000, 0x800
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CLK_SEL = 0x0000
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> SYS, 0, 1
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= RCHF, 0
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= DIV_CLK, 1
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> DIV, 1, 3
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= 1, 0
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= 2, 1
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= 4, 2
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= 8, 3
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= 16, 4
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= 32, 5
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> SRC, 4, 3
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= RCHF, 0
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= RCLF, 1
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= XTAH, 2
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= XTAL, 3
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= PLL, 4
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> W_PLL, 7, 1
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= RCHF, 0
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= XTAH, 1
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# The documentation doesn't match the firmware!
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> R_SARADC_SMPL, 9, 2
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= DIV1, 0
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= DIV2, 1
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= DIV4, 2
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= DIV8, 3
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> W_SARADC_SMPL, 10, 2
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= DIV1, 0
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= DIV2, 1
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= DIV4, 2
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= DIV8, 3
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> R_PLL, 11, 1
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= RCHF, 0
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= XTAH, 1
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DIV_CLK_GATE = 0x0004
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> DIV_CLK_GATE, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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DEV_CLK_GATE = 0x0008
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> GPIOA, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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> GPIOB, 1, 1
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= DISABLE, 0
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= ENABLE, 1
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> GPIOC, 2, 1
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= DISABLE, 0
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= ENABLE, 1
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> IIC0, 4, 1
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= DISABLE, 0
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= ENABLE, 1
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> IIC1, 5, 1
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= DISABLE, 0
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= ENABLE, 1
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> UART0, 6, 1
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= DISABLE, 0
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= ENABLE, 1
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> UART1, 7, 1
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= DISABLE, 0
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= ENABLE, 1
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> UART2, 8, 1
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= DISABLE, 0
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= ENABLE, 1
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> SPI0, 10, 1
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= DISABLE, 0
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= ENABLE, 1
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> SPI1, 11, 1
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= DISABLE, 0
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= ENABLE, 1
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> TIMER_BASE0, 12, 1
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= DISABLE, 0
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= ENABLE, 1
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> TIMER_BASE1, 13, 1
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= DISABLE, 0
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= ENABLE, 1
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> TIMER_BASE2, 14, 1
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= DISABLE, 0
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= ENABLE, 1
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> TIMER_PLUS0, 15, 1
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= DISABLE, 0
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= ENABLE, 1
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> TIMER_PLUS1, 16, 1
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= DISABLE, 0
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= ENABLE, 1
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> PWM_BASE0, 17, 1
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= DISABLE, 0
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= ENABLE, 1
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> PWM_BASE1, 18, 1
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= DISABLE, 0
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= ENABLE, 1
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> PWM_PLUS0, 20, 1
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= DISABLE, 0
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= ENABLE, 1
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> PWM_PLUS1, 21, 1
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= DISABLE, 0
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= ENABLE, 1
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> RTC, 22, 1
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= DISABLE, 0
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= ENABLE, 1
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> IWDT, 23, 1
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= DISABLE, 0
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= ENABLE, 1
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> WWDT, 24, 1
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= DISABLE, 0
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= ENABLE, 1
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> SARADC, 25, 1
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= DISABLE, 0
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= ENABLE, 1
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> CRC, 27, 1
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= DISABLE, 0
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= ENABLE, 1
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> AES, 28, 1
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= DISABLE, 0
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= ENABLE, 1
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RC_FREQ_DELTA = 0x0078
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> RCLF_DELTA, 0, 10
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> RCLF_SIG, 10, 1
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> RCHF_DELTA, 11, 20
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> RCHF_SIG, 31, 1
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VREF_VOLT_DELTA = 0x007C
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CHIP_ID0 = 0x0080
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CHIP_ID1 = 0x0084
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CHIP_ID2 = 0x0088
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CHIP_ID3 = 0x008C
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