ua1zbe
a1206d6fd4
Features: - VFO mode with direct frequency input - POCSAG decoder (512/1200 baud) with BCH(31,21) correction - Full-screen Spectrum analyzer - FM Radio receiver - RSSI signal indicator overlay - Custom boot splash (UA1ZBE / POCSAG pager / build date) Architecture: - app/mode.c — mode dispatcher (VFO/POCSAG/Spectrum/FM) - app/boot_splash.c — 2-second boot splash - app/pocsag/ — POCSAG decoder + BCH correction - app/display_rssi.c — RSSI indicator - main.c — entry point with custom init - syscalls.c — bare-metal _sbrk stub Build: arm-none-eabi-gcc -Os -flto -Wall -Werror -Wextra Size: 57.9KB Flash / 3.6KB RAM Controls: - 0-9: Direct frequency input (VFO) - SK2: POCSAG mode - SK1: Spectrum analyzer - 0: FM Radio - EXIT: Return to VFO - F/*: Toggle 512/1200 baud (in POCSAG)
170 lines
2.3 KiB
Modula-2
170 lines
2.3 KiB
Modula-2
# Copyright 2023 Dual Tachyon
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# https://github.com/DualTachyon
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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[DMA]
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@ = 0x40001000, 0x100
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CTR = 0x0000
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> DMAEN, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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INTEN = 0x0004
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> CH0_TC_INTEN, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH1_TC_INTEN, 1, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH2_TC_INTEN, 2, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH3_TC_INTEN, 3, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH0_THC_INTEN, 8, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH1_THC_INTEN, 9, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH2_THC_INTEN, 10, 1
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= DISABLE, 0
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= ENABLE, 1
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> CH3_THC_INTEN, 11, 1
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= DISABLE, 0
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= ENABLE, 1
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INTST = 0x0008
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> CH0_TC_INTST, 0, 1
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= NOT_SET, 0
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= SET, 1
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> CH1_TC_INTST, 1, 1
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= NOT_SET, 0
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= SET, 1
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> CH2_TC_INTST, 2, 1
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= NOT_SET, 0
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= SET, 1
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> CH3_TC_INTST, 3, 1
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= NOT_SET, 0
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= SET, 1
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> CH0_THC_INTST, 8, 1
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= NOT_SET, 0
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= SET, 1
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> CH1_THC_INTST, 9, 1
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= NOT_SET, 0
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= SET, 1
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> CH2_THC_INTST, 10, 1
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= NOT_SET, 0
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= SET, 1
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> CH3_THC_INTST, 11, 1
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= NOT_SET, 0
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= SET, 1
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[DMA_CH]
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$ = DMA_Channel_t
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CTR = 0x0000
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> CH_EN, 0, 1
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= DISABLE, 0
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= ENABLE, 1
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> LENGTH, 1, 12
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> LOOP, 13, 1
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= DISABLE, 0
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= ENABLE, 1
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> PRI, 14, 2
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= LOW, 0
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= MEDIUM, 1
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= HIGH, 2
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= HIGHEST, 3
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> SWREQ, 16, 1
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= SET, 1
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MOD = 0x0004
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> MS_ADDMOD, 0, 1
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= NONE, 0
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= INCREMENT, 1
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> MS_SIZE, 1, 2
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= 8BIT, 0
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= 16BIT, 1
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= 32BIT, 2
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= KEEP, 3
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> MS_SEL, 3, 3
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= SRAM, 0
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= HSREQ_MS0, 1
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= HSREQ_MS1, 2
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= HSREQ_MS2, 3
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= HSREQ_MS3, 4
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= HSREQ_MS4, 5
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= HSREQ_MS5, 6
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= HSREQ_MS6, 7
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> MD_ADDMOD, 8, 1
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= NONE, 0
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= INCREMENT, 1
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> MD_SIZE, 9, 2
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= 8BIT, 0
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= 16BIT, 1
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= 32BIT, 2
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= KEEP, 3
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> MD_SEL, 11, 3
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= SRAM, 0
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= HSREQ_MS0, 1
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= HSREQ_MS1, 2
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= HSREQ_MS2, 3
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= HSREQ_MS3, 4
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= HSREQ_MS4, 5
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= HSREQ_MS5, 6
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= HSREQ_MS6, 7
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MSADDR = 0x0008
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MDADDR = 0x000C
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ST = 0x0010
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[DMA_CH0]
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@ = 0x40001100, 0x20, $DMA_CH
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[DMA_CH1]
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@ = 0x40001120, 0x20, $DMA_CH
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[DMA_CH2]
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@ = 0x40001140, 0x20, $DMA_CH
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[DMA_CH3]
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@ = 0x40001160, 0x20, $DMA_CH
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